This invention relates generally to digital data processing systems, and, in particular, to a bus structure suitable for use with multiprocessor computer systems.
Multiprocessor computer systems provide multiple independent central processing units (CPUs) which can be coherently interconnected. Recent efforts in the multiprocessor field have concentrated on multiprocessor systems wherein each of a plurality of processors is equipped with a dedicated random access or cache memory unit. These multiple processors typically communicate with one another via a common system bus structure (i.e. shared bus systems), or by signalling within a shared memory address area (i.e. shared address space systems).
In recent years, a wide range of structures and methods have been proposed or developed to interconnect the processors of a shared bus system multiprocessor.
One such shared bus multiprocessing computer system is disclosed in United Kingdom Patent application No. 2,178,205 (published Feb. 4, 1987). That system is understood to comprise a plurality of processors, each having its own dedicated cache memory, and wherein the cache memories are connected to one another over a shared bus.
Conventional shared bus systems, however, lack adequate bandwidth to provide multiple processors with short effective access times during periods of high bus contention. Although a number of caching schemes have been proposed and developed for the purpose of reducing bus contention, bus saturation still limits the speed and size of multiprocessor computers.
Additionally, the speed of a conventional bus structure is limited by the speed of light and by bus length. In particular, as more processors are linked to a conventional bus, bus length increases and thus the time required for signal transfer increases.
Another class of interconnection systems, known as crossbar networks, avoid some of the limitations of conventional bus systems. In a crossbar network, however, the path taken by a given signal cannot be uniquely specified. Moreover, cost increases as the square of the number of interconnected processors. These characteristics make crossbar networks unsuitable for multiprocessor systems.
There accordingly exists a need for an interconnection system for multiprocessor computer systems which can accommodate the large volume of interconnect access requests generated by multiple processors. In particular, there exists a need for an interconnection system in which transfer speed is independent of the number of interconnected processors.
It is thus an object of the invention to provide an improved multiprocessor digital data processing system.
It is another object of the invention to provide an interconnection system for a multiprocessor digital computer structure which can provide multiple processors with short effective access times under all operating conditions.
It is yet another object of the invention to provide an interconnection system having the above characteristics which is applicable to both shared memory and non-shared memory multiprocessors.
It is a further object of the invention to provide an interconnection system having high bandwidth and the capability of transferring signals at rates sufficient to allow multiprocessors to operate at full speed.
It is another object of the invention to provide an interconnection system for a multiprocessor wherein bandwidth increases in proportion to the number of processors.
It is a further object of the invention to provide an interconnection system wherein transfer speed is independent of the number of interconnected processors, and is limited only by the switching speed of an individual interconnect.
Other general and specific objects of the invention will in part be obvious and will in part appear hereinafter.